Verification & Debugging Challenges In The Scalable Low-Power IP Subsystems

Abstract

Due to advancement in VLSI technology, transistors have been scaled down a lot incorporating more complex design in single System on Chip (SoC). As the complexity of designs increases, verification emerges as a dominant step concerned with time and cost in the development of a system-on-chip. Increased design complexity mandates the need for functional verification. The bug that is found at early level of abstraction will reduce the total cost incurred on a single chip so 70 % of the time is devoted in verifying the design. Aim of the project is to build a scalable verification infrastructure and verification component to meet the verification challenges faced during verification process and to increase the timing efficiency of the Verification Engineer in debugging. While verifying a complex design, many debugging challenges will be faced by a verification engineer. This report tries to discuss some of the verification and debugging challenges, faced during verification of a complex design and strategy to overcome this challenges.