ASIC Design of 8-bit 250MSPS Two-Step Flash ADC

Abstract

Modern wireless communication devices demand high data rate and low power consumption. The key components in the portable device which acts as an interface between analog and digital domains are Analog to Digital converters. As the demand for portable devices is increasing, more importance is given to the low power methodologies for high speed applications. Power consumption can be reduced by using small feature size processes. But as the power consumption reduces, process variations and other parameters affect the overall performance of the device. High speed, medium resolution and low power consumption are the major requirements in portable devices. The aim of this project is to design an 8-bit 250MSPS ADC. It is a mixed signal ADC ASIC. The architecture chosen for this design is sub-ranging type 2-step flash ADC. The ADC is designed in two steps of 4-bit flash type ADC.ADC design consists of sample and hold block, comparator block, op-amp, bias circuit and TGB encoder. Sample and hold design is implemented using switched capacitor logic and it also consists of an operational amplifier (opamp). A general purpose op-amp is designed which could be used in 3 different modules of ADC, S/H amplifier, Subtractor and Residual amplifier. After in-depth analysis of different op-amp topologies with reference to given specifications, Two Stage Folded Cascade topology is selected.The comparator is of clocked type. The ADC has been designed, implemented and analyzed in 180nm technology using Cadence Virtuoso 6.1.5 in spectre simulator.