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DC Field | Value | Language |
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dc.contributor.author | Patel, Anal | - |
dc.date.accessioned | 2019-08-30T09:28:04Z | - |
dc.date.available | 2019-08-30T09:28:04Z | - |
dc.date.issued | 2018-06-01 | - |
dc.identifier.uri | http://10.1.7.192:80/jspui/handle/123456789/8808 | - |
dc.description.abstract | Passive components play very important role in the microchips for radio frequency ap- plications. Particularly Inductors which are used in the most common circuits in RF ICs like low-noise amplifiers and oscillators. For lower frequency, we can connect an inductor externally. But at higher frequency even a single wire will have some value of inductance, resistance and capacitance so external inductor won't have the same value of inductance practically. Because as frequency increases the parasitic capacitance, parasitic resistance and all other high frequency effects will come into picture. Hence the idea of integrated inductors took place. To design an integrated inductor for RF application is a very critical task because there will always be a trade-o among inductance, quality factor or resonant frequency. The optimization of geometric parameters can improve its performance. In this work a lumped physical model is explained which represents the characteristics of an on-chip inductor at higher frequencies. The figure of merits of integrated inductors such as quality factor, self resonant frequency, etc. depend on the layout parameters. There will always be a tradeoff between the performance of a spiral inductor and its layout parameters. In this study the layout parameters are chanegd and the effect of those changes over figure of merits are observed and discussed. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 16MECC07; | - |
dc.subject | EC 2016 | en_US |
dc.subject | Project Report | en_US |
dc.subject | Project Report 2016 | en_US |
dc.subject | EC Project Report | en_US |
dc.subject | EC (Communication) | en_US |
dc.subject | Communication | en_US |
dc.subject | Communication 2016 | en_US |
dc.subject | 16MECC | en_US |
dc.subject | 16MECC07 | en_US |
dc.title | Design and Modelling of an on Chip Inductor | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EC (Communication) |
Files in This Item:
File | Description | Size | Format | |
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16MECC07.pdf | 16MECC07 | 1.82 MB | Adobe PDF | ![]() View/Open |
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