Memory BIST Implementation and Validation

Abstract

Testing is very important aspect of any VLSI product. Compromise in testing directly affects trust of people on product and company. As SoCs are becoming more complex day by day DFT has very important role in the design. In fact, DFT is expanding as the technology is shrinking. As the technology is scaling down (28nm, 22nm, 14nm, 10nm etc.), this introduces manufacturing challenges and also higher chances of failure and Crosstalk effects. Chips can fail after manufacturing due to Contamination causing open circuits, Extra metal causing short circuits, Insufficient doping, Open interconnect on the die caused by dust particles. When manufacturing defects occurs, the physical defect has a logical effect on the circuit behavior and chip may not work as intended. Detecting faulty chips is more costly in the later stages of life cycle of the product. So, it is needed that the device which are shipped to the end customer are not defective one. So, before shipping to the end customers, the manufacturing defects must be tested, to filter out the bad device with the good one. Memories are more vulnerable to physical defects than logic circuits because of their higher density and more complicated processing steps. Memory BIST is a digital logic, which is inserted in the design, to detect all the defects present in the memories arrays caused during manufacturing process. Memory BIST hardware incorporates various test algorithms to targets these defects. This thesis covers MBIST architecture in brief where description for all the blocks is included,the flow of Memory BIST insertion at wrapper level and creation of the TAP controller RTL based on fullchip requirements. It also covers how to generate testbenches/patterns that can be used for pre and post silicon validation. Memory Rastering process is included which will help to find the loaction where exactly the memory is failing. This thesis also helps to understand the post MBIST simulation debug process.