A Built-in Self-Test with Design for Testability Support for Embedded SRAM

Abstract

The motivation of this project is to improve the testing methodology by providing low cost in-built feature like Built-In Self-Test in terms of power, area and speed which can make testing easy.With the increasing number of embedded memories in the modern system-on-chips (SOCs) and increasing number of transistor on embedded memories, the cost of memory testing becomes significant. Increasing number of transistor on embedded memory leads to the manufacturing defects as the number of transistor are closely placed on the silicon, probability of transistor being faulty is increases, so Built-in-self-test (BIST) is an effective technique for memory testing. The drawback of using BIST is the penalty in the performance as extra hardware will require additional area and that will lead to more routing and hence more area but considering the advantages of BIST, every designer chooses to use BIST. So, understanding of BIST becomes important for better design. In the high density memory, probability of the transistor getting faulty also increases and that would result in lesser yield. To increase the yield, Built-In Self-Repair (BISR) technique is used which is also known as Redundancy.The penalty of using this additional feature of memory is its performance. More area is used because of the redundant hardware and this will also give its impact on power and timing.