Comparative Analysis and Evaluation Of Different CMOS Technologies

Abstract

Over the past decades perpetual shrinking of devices and circuits has led to semiconductor product improvements. A paralleling trend is that process variations and intra-die variability increase with each technology node and controlling the manufacturing process is very difficult. these fluctuations cause device and circuit characteristics to deviate from design goals and introduce significant device-to-device variability.The decrease in size of CMOS transistors leads to miniaturization of wires connecting these devices. However, there is a steep rise in the current density across integrated circuit. The increased current density eventually raises concern that VLSI chip reliability may be adversely impacted due to EM induced failures in the interconnects.Also,increasing design complexity, tighter design cycle time and performance requirements of advanced nanometer VLSI designs have made power/performance/area estimations at an early design phase critical design steps. So, accurate modelling of these early estimations, process variations and reliability issues has become critical to both foundries and circuit designers that seek optimal PPA balance. To address time to market issue FOM (figure of merit ) analysis is performed on different CMOS process which gives performance and leakage estimations at different PVT’s ,VT/CL’s very early in the design cycle. The impact of process and voltage variations has been analysed by running monte-carlo simulations on different technology nodes. Also, cell level variation is performed using regressive hspice simulations which gives us a estimate of manufacturing yield. Reliability analysis of different cells is performed with emphasis on electromigration estimation in power and signal lines. EM checks are performed to identify which cells satisfy the foundry EM and power on hours requirement.