Robust Timing Analysis & Modelling of Custom High Speed Serial IO Blocks

Abstract

Major design challenges of ASIC design are ultra-high speeds, power dissipation, supply rail drop, interconnect, noise, crosstalk, reliability, manufacturability and the clock distribution. On Chip Variation (OCV) is one of the barriers which contribute to these challenges and its effects are increasing with smaller process node. With lower technology node, clock tree robustness has become an even more critical factor affecting SoC performance. Conventionally, our focus is on designing a symmetrical clock tree with minimum latency and skew. Another design challenge is the effect of crosstalk, which plays an important role in the signal integrity of the design. Crosstalk analysis are used to make the ASIC behave robustly from a timing perspective. The design functionality and its performance can be limited by noise, will impact on frequency of design and also causing functional failures. To mitigate the above discussed issues like crosstalk and clock tree distribution it needs to devise some new methodology which provides improvement to increase robustness of the design against variations. In this thesis we focus on one such methodology which is clock mesh technology. Clock mesh technology provides uniform low skew clock distribution and offers better tolerance to on-chip variations (OCV) than conventional clock tree technology. Output slew analyzed on clock buffer clock inverter considering RC impact. Also cross talk analysis is done for various metal length and layers with different spacing, which will give the constraints on the maximum length to be used for routing.