Pre-Silicon Verification of Design For Debug Logic in SoC

Abstract

Pre-silicon verification techniques in use, cannot assure that all the bugs in software as well as hardware are spotted and removed before actual implementation of the design on silicon. In an analysis in the year 2007, it was observed that industry spends half of the total project duration in post-silicon validation and debugging.Design for debug methodology, helps in the speeding up post silicon debug by improving the internal signal observability of various system layers. The scope of this work is the coverage of such design for debug logic implemented to SoC for tracing internal signals and for accessing registers of SoC partitions during post silicon validation and debugging.The verification part related to implementation of these logic are emphasized more in this documentation. Adding to the above verification strategy and SV written for the same, some scripts(in Perl) are also included to aid faster debug of RTL simulation issues.