Improvement of Project Turn-Around Time using In-design IR/RV Analysis

Abstract

With ever increasing emphasis on project time lines, it is imperative to identify design cycles which take majority of time and find an innovative solution to the problem. One such issue is Volatge Drop/Reliability Verification (IR/RV) signofi which can potentially delay the tape-out by weeks. In general, the total time taken to generate layout from synthesized netlist is around 4 to 5 days and thereafter to generate IR Voltage Drop (IR), Electro-Migration (EM) violation report is around 2 to 3 days. These violation reports are analyzed to fix the design and generate the new layout. Each such cycle takes approximately 1 week. A violation free layout of the design is generated after multiple such cycles. To reduce this turn-around time, we are trying to enable the IR/RV analysis from within the Place and Route (PNR) tool, called as In-Design tool. This will help designer to get violations at any/every stage in the design. This tool will help designer to debug and fix violations in the design stage by stage, completing the layout and its IR/RV signofi in 4 to 5 days as compared to multiple weeks. For enabling IR/RV analysis from within the PNR tool, the newer version of PNR tool having inbuilt IR/RV analysis tool is correlated with standalone IR/RV analysis tool. This allows designer to do IR aware Placement as well as IR aware routing by doing IR/RV analysis before and after placement as well as routing. This reduces the design turn-around time helping designer to meet project deadline.