Scalable Integration,Verification ow for faster Soc Build Up

Abstract

VLSI technology is advancing day by day, transistors have been scaled down a lot incorporating more complex design in single System on Chip (SoC). Now a days the complexity of chip is rapidly increasing, verification plays a dominant role concerned with time and price in the enhancement of a Soc. Increased design complexity mandates the need for functional verification. The bug that is found at early level of abstraction will reduce the total cost incurred on a single chip so 70 percent of the time is devoted in verifying the design. Even though SOC requires multi-instances of IP integration and verification collateral, the IP development methodology is built for a single instance and this introduces unique challenges at SOC. Numerous challenges arise when the IP en- vironment is stamped multiple times with regards to RTL, Test bench, test Island collateral integration and IP validation, resulting in long integration and debug cy- cles. This report addresses the SoC problem of integration of IPs by providing a mini SoC framework, which delivers scalable integration (collage and testisland) collateral capability, exible reconfiguration of the verification environment. This report also presents key learnings and challenges encountered during development of the Multi-Instance (MI) SoC-Subsystem. This proof-of-concept subsystem was successfully deployed for PCIE Multiple Virtual Channel (MVC) IP and reused for PCIE Single Virtual channel (SVC).