Migration of MEM ACS to Automated Simlist Generation Flow

Abstract

Verification and design analysis are major components of microprocessor design cy- cle time, any effort that improves verification effectiveness and design quality is crucial for meeting customer deadlines and requirements.It is well known to all IP creators and customers that function verification is a very big problem in semicon- ductor industry. As complexity of design increases, need of verification effort is more compare to design effort. For ARM CPU cores IP’s which is a complex IP, it is difficult to detect desing errors and provide more validation coverage. Functional validation is one of the mostly known bottlenecks in System-on-Chip (SoC) design cycle. A mojority of engineering effort is spent on validating the SoC. According to Wilson Research Group, 57 percent time is spent of validation of a SoC project. Therefore optimization of validation flow is crucial for complex IPs such as ARM CPU Architecture.In this report a part of entire validation flow of ARM V8A ar- chitecture is optimized to reduce simulation time and complexity of system.In this work MEM suite of ACK kit is taken in to consideration for optimization, different MEM suites are migrated to a new validation flow that will directly link the simlist generation to the target configuration parameters.