Development of SoC Architecture Validation Framework

Abstract

System-on-Chip (SoC) architecture validation is a process of finding the optimal design of the architecture for given requirements. As the quantity of intellectual property (IP) modules in SoC increases, it is critical to validate the performance at an early stage. System level model helps to explore architecture and achieve an early verification. The ultimate goal is to measure performance KPI for modem SoC. Programming languages such as C and C++ can be used for software simulation or to create test bench. HDL languages like Verilog and VHDL are used for describing hardware. SystemC is a library of C++ which can be used for both creating test bench and describing hardware without compromising key performance indicator (KPI) requirements. Transaction-level modeling (TLM) is implemented as a layer on top of IEEE 1666TM SystemC. TLM uses function calls to communicate over a set of channels, describing a system-level model in an abstract manner. Hence leading to faster simulation speed while offering good accuracy.

Transaction level approximately-timed analysis is used for accurate analysis in per- formance model framework to validate SoC architecture. Performance modeling of

SoC consists of modeling and analysis of SoC considering parameters like network capacity, latency and speed. For performance modeling, the connectivity test is performed to measure latency, bandwidth and theoretical throughput on each and every possible initiator-target path using automated Perl scripting. File-based traffic patterns are simulated in the regression framework for KPI measurement.