Timing Closure of Partitions for Lower Technology Nodes

Abstract

Metal interconnects basically used for make the interconnections between different part of the circuitry in order to realize any System on Chip (SoC) design. These metal interconnects affect the performance of the design as the process technology drastically shrinks. For nanometer process technologies, the coupling effect in the interconnect causes noise and crosstalk. These noise and crosstalk can affect the operating speed of the design, which is responsible for the timing aspect of the design. These problems are negligible in the older technologies. Thus, the physical design and verification of latest process technologies should include the effects of crosstalk and noise. If the timing of a design is not verified, then the design may not perform at the desired operating speed it was designed for. Apart from timing there are two other factors that needs to be considered while designing. Those are Power and Area. There will always be a trade-off between these three factors. Static Timing Analysis (STA) is one of the many techniques used by the designers to verify the timing of the design and also for closing the design with respect to timing, which is called as timing closure. There is one more method called Dynamic Timing Analysis (DTA) or Timing Simulation, which was used in older days for timing verification. STA is static because the analysis is done when the design is stable and it does not depend upon the input vectors being given to the design. STA uses setup check and hold check for verifying the timing of the design. Synopsys PrimeTime is the tool used for STA. During the physical implementation of the design (Pre-Signoff/ICC stage) also the timing can be optimized by using efficient floorplanning, placement and routing techniques. Most of the timing optimization are done in physical implementation stage only. Synopsys IC Compiler II is the tool used for the physical implementation. The main aim of this master thesis is to investigate various timing optimization techniques and methods to fix the timing violations in both pre-signoff and signoff stage. In signoff stage, the design will be in Engineering Change Order (ECO) mode and there will be no further design optimization performed in this stage.

The timing fixes are given in the form of ECOs and those are sourced and routed. The tech- niques that are used in this stage are cell sizing and buffer insertion. Only in the pre-signoff

stage, optimization of the design is done by changing the floorplan, placement and route of the design. In both the stages of timing optimization, power and area of the design will also change and hence they should also be checked and maintained within limits. These techniques and methods are analysed and implemented to achieve better timing results and ultimately to validate the operating speed of the design.