Customized Routing Optimization Flow To Fix Timing Violations in Ultra Deep Sub Micron Technology

Abstract

In ultra-deep submicron technology, Routing has become challenging due to the ever- increasing number of metal layers, distinct layer thicknesses, new design rules and design complexity. Due to increase in congestion with lower technology nodes designer has to predict during floor plan weather routing is possible with meeting timing constraints. It is not enough to route only but need to route with DRC clean and without degrading post layout timings. Due to area reduction with lower node technology, routing congestion increases on chip and in that scenario need to route the different topologies for the single net. Best topology need to be routed and for that topologies timings are calculated for that path and if it is not meeting there are some methodologies in Layout which will fix the timing violations for the routed net. This thesis will discuss about routing a net with different routing topologies and from all those we can select the best topology which meets our timing violations and DRC re- quirements.Flow is developed which will select the best topology from available topologies on the basis of different criteria and which will be routed automatically with given metal layers.Once it is routed, It will also fix the timing violations on the net with different layout solutions.