Optimization of a Component IP within an Infrastructure Subsystem

Abstract

Arm being a Semiconductor IP company, is a pioneer in market for providing IPs which are used in numerous field of SoCs such as arm based processors in automobiles, IoTs,servers, mobiles and lately in machine learning chips as well. Functional validation for these IPs is one of the challenging task in today’s

scenario as the heterogeneous complexity of SoC design has increased consid- erably.But, before delivering these IPs to numerous Arm Partners,verification

of these ARM IPs focuses on extensively validating the inter working of multi- ple ARM IPs in a wide variety of practical kind of systems with wide range of

configurability and scalablity which in arm environment is abbreviated Kits. With robust verification methodology of IP under the SoC environment helps us to detect bugs at an early stage of design cycle which can detect more

bugs comparatively to only functionally verifying IP alone.Main challenge ly- ing here is integrating various IP components within the System, is to achieve

a target system performance with minimum resource allocation.So the main objective underneath is to understand the functionality of each module of base element(IP) of infrastructure SoC environment and knock out the additional logic’s and modules used as well migration the STM(System Trace Macrocell)

from base element to the dedicated Debug IP and thus achieving faster per- formance,lower gate counts,LUT’s and validate it in a designed dedicated test

suite environment. Being a part of Kits team as well as Memory modelling team, this dissertation also includes project work from memory modelling team

where the primary objective was to write a generic test bench for the mem- ory compiler validation suite to achieve the maximum functional coverage for

testing each pins of sram memories. All the simulation and as well as the emulation results are included in this thesis.