Design and Analysis of Frequency Synthesizer

Abstract

The frequency synthesizer is the most versatile application. The Application of fre- quency synthesizer is clock generation and clock recovery in microprocessor.In thesis

this, design and implemented of an individual block of the frequency synthesizer. In order to improve the frequency synthesizer performance, the different technique will be used and all this technique are discussed. In this thesis, frequency synthesizer first block is designed is charge pump. The main of the CP is to improve matching current, leakage current and wide range of the output voltage. The design of CP

is proposed and simulated in the cadence virtuoso tool at sbc 180nm CMOS Tech- nology. The design of NMOS cascode CP is achieved wide range output voltage

swing at 0.4 to 1.2 V and improves mismatch current using this cascoded charge

pump. Voltage controlled oscillator is the most important block in a frequency syn- thesizer. In this thesis, we design a single-ended ring oscillator with 0.5GHZ to

1.17GHz tunning range has been designing with the total power consumption of the VCO is 6.8mV and the phase noise -110.92dBc/Hz at 1MHz frequency offset. In

the thesis, we are also design differential ring oscillator with 1GHZ to 2GHz tun- ing range, with the power consumption of the VCO is 8.7mW and the phase noise

-114.2dBc/Hz at 1MHz frequency offset. In this thesis, we are designing a 6-bit multi-modulus frequency divider and It can work up to 3GHz operating frequency where power supply is 1.8V. The division ratio can be varied from 64 to 127 and it can be achieved using the MMD technique. In multi-modulus frequency divider The main block is 2/3 prescaler and it’s designed using TSPC D-FF logic. In the future with an incremental step of one the proposed multi-modulus frequency divider is suitable for sigma-delta fractional-N frequency synthesizer implementation.