SoC Power Management Validation

Abstract

Every design verification technique requires coverage metrics to assess the quality of the design and determine when the design it is robust enough for tape-out. This project

contains the functional coverage collection flow of full chip power management and ap- proach to increase the Coverage Percentage. At end of the Project Coverage Percentage

of 88% is achieved. This project also explains about the debugging of the full chip power management test cases through emulation.

First step towards the coverage collection of FCPM is get all the scenario to be tested. During this project test plan document is prepared consisting of all the scenario as Power states are the major functionality that need to be covered are identified and added in coverage module of the Power Checker.

After running the test case , Power Checker runs on post processing mode to generate the Virtual Database. This database has the coverage information. All the database of the individual test cases in the project are combined into one database to get consolidated coverage information and final database is used to analyze missed cover items.

There are many approach to analyze missed cover items. In this project few of the approach are discussed. Missed cover items are analyzed through simulation waveform. Uncovered items are to be covered through identifying proper test case. Sometime cover

items are missed if required switches or fuses are disabled on SoC. These fuses are re- sponsible for enablement of particular functionality on the SoC.

During the entire flow, many tools are used. Verdi- Coverage Point viewer is used to check which missed and hit covered items. Verdi is also used to see the simulation waveform. Urg is used to combine all the database of different test case into one.