Power and Leakage Saving Technique in Memory

Abstract

The performance and cost of an ASIC depends heavily on the quantity and quality of embed- ded SRAM included in the design. SRAM memory, there are still several options available to

configure the memory instances to dramatically reduce cost or improve performance. If these configuration options are either unavailable in the memory compiler or are not chosen properly,

the overall design will suffer. Power and Leakage plays a major role to check the product qual- ity before it goes to market. While advanced Pre-Si Quality Assurance checks can catch design

errors, it can miss physical bugs which can only be identified by Post-Si validation. Today, low power memory is given most priority in VLSI design. Low power feature for on-chip SRAMs is becoming increasingly important, especially for battery-operated portable application. So,

the power reduction for one cell is the vital role in memory design techniques. As the technol- ogy growing portable device (e.g. Cell phone, PDA) increases, the Static Power Consumption

(Leakage Power) and dynamic power became a significant issue. Leakage current in standby mode is the major part of power loss. SRAM continues to be an important macro block of SoCs. There is some technique through which we can reduce the power dissipation like by using dualrail voltage, address decoding schemes, assist technique, by applying different rmi

settings, power gating, etc. Analyzing the memory operation by applying different power sup- ply to periphery and array by inserting level shifter in design and read and write margin is very

important to achieve also done some analysis by changing wordline and bitline voltage and try to reduce leakage in memory and also analyze the 6T SRAM parameters and 6T SRAM with different schemes to achieve less leakage and power.

This thesis outlines the architecture of the Memory Chips and its Design Flow and how the efficient methodologies have been proposed for reducing leakage current and Power in Memory design. Its built to check behavior of chip with the different technology on die. The thesis will focus more on the various approaches used for Pre-Silicon Power and Leakage Saving strategy for the Memory based Designs and extend the lifetime of digital circuits.