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dc.contributor.authorMali, Bhoomika-
dc.date.accessioned2020-07-20T05:50:59Z-
dc.date.available2020-07-20T05:50:59Z-
dc.date.issued2019-06-01-
dc.identifier.urihttp://10.1.7.192:80/jspui/handle/123456789/9156-
dc.description.abstractIn SRAM design, more challenging task to improve SNM (Static Noise Margin) and WM (Write Margin). In this thesis i used Read and Write Assist technique to improve my WM and SNM in memory. In our memory there is more challenges at lower technology. When we go at low technology at that time some margin voltage will change according to our requirement. So for that we used assist technique to improve this things in memory. Basically we used assist technique when my read and write operation is fail. In my memory during read operation my read is fail some time because of size and some param- eter like voltage etc. For that i have to use read assist technique because my stability is so poor some time because of size problem so i got bad SNM in my memory. To reduce my SNM we changed in design like size change or Vt change and after that i used technique and got better SNM using WL Boosting technique. During write operation, i got bad WM or some time i got write data very late time so i got failure in write operation. For that i used technique which is Negative Bit-line technique. In this i give some dip voltage according to our requirement and got better WM (Write Margin). Read failure occurs when the cell is not able to preserve a zero and that is possibly because the pass gate becomes too strong as compared to pull down and trip point of the opposite inverter shifts towards 0, because of the weak PMOS and strong NMOS. Write Failure occurs when the cell is not able to create a regenerative effect and flip the state of the cell and that is possibly because the pass gate becomes weak as compared to the pull up which inhibits the node voltage to go below the switching threshold and flip the state. So, the current through the transistor decreases and the effects of threshold voltage fluctuation cannot be neglected at lower supply voltages. The limitation on the minimum operating supply voltage Vmin is critical and require circuit assist techniques to enhance the functional window of the cell.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries17MECV18;-
dc.subjectEC 2017en_US
dc.subjectProject Reporten_US
dc.subjectProject Report 2017en_US
dc.subjectEC Project Reporten_US
dc.subjectEC (VLSI)en_US
dc.subjectVLSIen_US
dc.subjectVLSI 2017en_US
dc.subject17MECen_US
dc.subject17MECVen_US
dc.subject17MECV18en_US
dc.subjectRA (Read Assit)en_US
dc.subjectWA (Write Assist)en_US
dc.subjectFloorplanen_US
dc.subjectWM(Write Margin)en_US
dc.subjectSNM (Static Noise Margin)en_US
dc.titleVariation Tolerant SRAM Write and Read Assist Techniqueen_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, EC (VLSI)

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