Design and Characterization of I/O cells compatible to I2C Bus

Abstract

The input/output circuits (I/O) are essential to VLSI chip design. The design quality of these circuits is a critical factor that determines the reliability, signal integrity and interchip communication speed of the chip in a systems environment. If the package is considered a protection layer of the silicon chip, then the I/O frame containing input and output circuits can be considered as a second protection layer. The basis of the project is to perfect the design over variation in Process, Voltage and Timing. I2C bus plays important role For Inter-IC control. It maximizes Hardware efficiency and circuit simplicity. IO cell which consist Various buffer, Filter and many other components provides proper signal between core and External environment. Characterization involves Analysis of delay, effect of output slope, at difference PVTSC. This project basically consist review of the need for I/O cells and design of Input buffer Compatible to I2C bus and Output Buffer . Activity of this Project is concerned with design of cell according to Specification and make sure of result by simulation. Characterization at various condition will provide information about the deviation between specified value and obtained results.