Boundary Scan Validation For SoC

Abstract

As printed circuit boards (PCBs) has become more complex and denser, the need for exhaustive testing becomes extensively important. The IEEE 1149.1 Boundary Scan Architecture provides access to internal module network required for interconnect testing in situations where physical access is sparse or not possible. As the advantage of boundary scan was becoming recognized in many commercial applications, it became apparent that a universal definition was needed to achieve the economies of using as industry standard. This led to the 1990 approval of IEEE Standard 1149.1. It gives standardized approach to testing interconnection between integrated circuit, testing integrated circuit itself and observing and modifying circuit activity during component’s normal operation. Boundary Scan architecture tests pin connectivity without using physical test probes and captures functional data while a device is functioning normally. A set of test cases is defined, such that the component can respond to a set of instructions designed to support testing. Typical Boundary Scan testing involves manually generating bsdl file and test cases and then validating the model.This report describes the limitation of this method and suggests an alternate, automated ,efficient and faster approach to Boundary Scan testing validation.