Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/9381
Title: Metal Layer Pattern Detection
Authors: Bhavsar, Tithi
Keywords: EC 2018
Project Report 2018
EC Project Report
EC (VLSI)
VLSI
VLSI 2018
18MEC
18MECV
18MECV02
Issue Date: 1-Jun-2020
Publisher: Institute of Technology
Series/Report no.: 18MECV02;
Abstract: Chemical Mechanical Planarization (CMP) is a polishing process that does chip planarization to remove excess surface materials using chemicals. However, post CMP local and global planarization of the chip depends on the layout pattern density. To ensure that metal density is evenly distributed on the entire chip, insertion of dummy metal fill in the less dense areas of the design is important. To automate this process of dummy metal fill, the tool initially needs to detect all the existing metal layers of the design in order to avoid unwanted shorts with the signal lines and other DRC violations. This makes Metal Layer Pattern Detection an important stage to make sure that no violations occur post dummy metal fill. In this paper discusses about Pattern Detection Engine (PDE) which is used to determine metal tracks in the design. Pattern Detection engine is the flow that detects metal patterns existing in the design and based on it decides which metal pattern can be placed in the white space region in between the existing metal patterns. These patterns are determined using Constraint Programming of CPLEX optimizer which gives an optimal solution in terms of transition patterns i.e. the pattern that can be placed between the existing metal track patterns. Apart from the PDE flow, this paper also discusses various new methods developed to improve the metal fill results in terms of both DRC’s and Density violation. Also, there were new techniques like bounding box and incremental fill enabled to help users in the ECO stage, prior to final sign-off of the design. The new PDE flow developed could solve minimum density violation efficiently. Also, many DRC violations could be solved with new PDE flow as it added metal patterns as per the metal rule book. Bounding box and Incremental fill techniques reduced the manual efforts that a designer might need to take before running fill and thus helped them to reach sign off stage for their design faster.
URI: http://10.1.7.192:80/jspui/handle/123456789/9381
Appears in Collections:Dissertation, EC (VLSI)

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