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http://10.1.7.192:80/jspui/handle/123456789/9389
Title: | Post Silicon Validation of DC-DC Boost Converter Analog IP |
Authors: | Patel, Mayurkumar |
Keywords: | EC 2018 Project Report 2018 EC Project Report EC (VLSI) VLSI VLSI 2018 18MEC 18MECV 18MECV10 |
Issue Date: | 1-Jun-2020 |
Publisher: | Institute of Technology |
Series/Report no.: | 18MECV10; |
Abstract: | The thesis work is on post-silicon validation of Boost convertor Analog IP during the internship period. DC-DC booster is analog IP which is used for DC voltage scaling with reference to input voltage. Voltage scaling is dependent on the duty cycle of the switching of MOSFET. Control signal of Analog IP comes from digital control block. For validation, digital part of Booster IP is prototyped inside the FPGA and analog IP is mounted on Validation board. Validation Test cases for IP are derived from Test specification of IP, and then test cases are categorized into characterization test, functional test, validation test, robustness check etc. All these tests are performed with help of expensive lab equipment such as Mixed signal oscilloscope, Function generator, Power supply, Source meter, thermostream under controlled environment. The results of test cases compared with test specification and the results out of specs were reported back to designer for improvement in Second tape out. To build up pre-silicon validation platform, FPGA Prototype of digital RTL implemented with model of analog IP. FPGA prototyping helps in pre silicon phase for validation bring up, software development and FPGA verification. FPGA based Validation can provide a demonstration for downstream customers, providing confidence the system is functioning as specified. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/9389 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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18MECV10.pdf | 18MECV10 | 2.34 MB | Adobe PDF | ![]() View/Open |
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