Boundary Scan Verification

Abstract

This project aims for the verification of boundary scan architecture in any design for detecting bugs at an earlier stage while maximizing product quality. As the technology node reduces, the device becomes faster and the complexity of the chip increases. The reduction in feature size increases the probability of manufacturing defects in an Integrated Circuit. Thus, it is significant to test the IC once they are taped out. To address the testing challenges for the physical defects, DFT (Design for test) architecture has become popular in the industry. Boundary-scan is one of the DFT embedded in the chip to address the testing challenge between interconnects of the chip. Functional verification of the implemented boundary scan in the design is essential to make sure that the design works the way it has been intended to perform. Many tools aid in the design verification including simulation tools and test content generation automation tools dedicated to boundary-scan. The test stimuli and testbench are generated using the Mentor Graphics Tessent tool. The test patterns are completely derived from the BSDL (Boundary-scan description language) file which provides a complete description of the boundary scan implemented in the device, no other design data is used in doing so. The test patterns are validated by integrating into the OVM (Open Verification Methodology) testbench environment dedicated to the validation of the TAP (Test Access Port) architecture. The test case covers all possible test scenarios needed to test the different instructions of boundary-scan. This validates the boundary-scan architecture and BSDL file at the IP (Intellectual Property) level. The methodology is used to make all BSDL and boundary-scan validated individually executed at the IP level so that it provides consistent verification of boundary-scan implemented at SOC (System on Chip) level. The testbench using OVM increased the reusability and can be used at any level of the hierarchy.