Verification of Ethernet based IP/Subsystem in Smart NIC

Abstract

Verifying system is very important aspect from the cost perspective, time to market is greatly impacted by it. As silicon-chip is becoming more complex, nowadays it is very demanding that we achieve completeness in verifying design on or before desired time. There are two categories for verification process - the first one is tool-based process and the second one is different methods of verification. Demand for proper guidelines of different processes and methods are escalating to achieve good quality of verification. What need to be done is about processes and how to be done is about methods. During my project work industrial process are followed for verification of single module in the IP. Developing robust, reusable and highly configurable structure is described here. Important aspects and key points while following process of verifying design is described here thoroughly. Impact of configurations provided in the module level structure on the subsystem level structure is explained. Design behaviour under different excitation is studied thoroughly as prerequisite of the verification process. Highly configurable verification structure is developed, to make it reusable. To cover all the corner cases for module, testplan is prepared and maintained the verification process. Also, functional coverage plan is prepared to ensure required coroner cases are covered in the verification process. During project work, I studied important aspects of subsystem that is mainly focused during verification process. At this level, mainly top-level interface related coverage are coded, other required coverage is collected from sub-block. For subsystem coverage tracking HVP is maintained, also all coverage is coded using proper methods, so that only required coverage can be enabled keeping others disabled. To achieve verification closure, we need coverage numbers up to the marks, for that we run regression on weekly basis to generate high randomization. This repetitive work is automated using perl automation script. That can generate report for better bucketization of errors and failures. In the later part of thesis sim profiling is described for improving real time of simulation. Thesis also shows different performance testing scenarios generated for the subsystem to eliminate performance bottlenecks.