Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/134
Title: Structured ASIC: Evaluation and Implementation
Authors: Patel, Manish U.
Keywords: EC 2005
Project Report 2005
EC Project Report
Project Report
05MEC012
05MEC
VLSI
VLSI 2005
Issue Date: 1-Jun-2007
Publisher: Institute of Technology
Series/Report no.: 05MEC012
Abstract: Structured ASIC is very latest concept in the field of Configurable Logic. It bridges the gap between FPGA and Standard Cell based Design hence having advantages of both. With an optimized and programmable structure, the structured ASIC technology indeed introduces a dramatically reduce ASIC cost and manufacturing turn-around time. The structured ASIC implementation flow is more complex than the conventional cell-based flow. This project explore the differnt Structured ASIC architecture and Implement variuos designs on available Structured ASIC core like eASIC, ViASIC and LightSpeed hence customer can get best option for their Silicon Implementation. This report compares eASIC, ViASIC and LIghtSpeed architecture goodness using experimental techniques. Comparison is made with respect to each other in terms of frequency, utilization and capacity. As the design flow is complex various design issues encountered during the flow which may not occur in the ASIC flow. These issues are discussed and remedies for the same also proposed.
URI: http://hdl.handle.net/123456789/134
Appears in Collections:Dissertation, EC (VLSI)

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