Design, Analysis and Performance based Evaluation of DLL (Delay Locked Loop) in DSM Technology

Abstract

Currently, CMOS VLSI is progressing at fast rate for decades and dominatingmost of markets in digital circuit areas. In a constant voltage scaling, the vertical andlater electric elds are increased, which reduced to oxide reliability. Low power supplyvoltage is required necessarily. For the design of CMOS VLSI systems using lowpower supply voltage, the implementation of chips is directly limited by processingtechnology and devices. The objective is to demonstrate the useful techniques inthe designing of logic level and system building blocks in low-voltage CMOS VLSItechnology.Generation and distribution of clock signals inside the VLSI systems is one ofthe most important problems in the design of VLSI systems. Because of the processvariations and interconnect parasitic, clock signals delays vary for dierent paths. Theclock signals should have zero clock skew, that is to say all the clock signals shouldarrive at the inputs of registers at the same time. Otherwise latches and ip-ops'get clock signal at dierent time instances. In order to circuit to operate correctlythese dierences should be eliminated, ideally to zero. However it is not possiblepractically and 10 percentage of the clock cycle is expended in order to compensatefor clock skew.Delay Locked Loops (DLL) are widely employed in microprocessors, memory, andcommunication ICs in order to reduce on chip clock buering delays and improve I/Otiming margins. A DLL is a digital circuit similar to a phase-locked loop, with themain dierence being the absence of an internal oscillator. A DLL can be used tochange the phase of a clock signal.