Design and Optimization of the Algorithms and the Data Structures used in the Chip Analysis Tools

Abstract

This project aims to minimize the time and space complexity required in the chip analysis tool. To minimizing the complexity various algorithms has to be implemented and the various tactics are applied at the various level of implementations. These algorithms and tactics are described in the thesis. Following chip analysis tools has been optimized at various levels.  Component Descriptor Language Utility  Timing Power Product tool  CDL Verilog comparison tool  Pattern Search engine A new data structure is designed for Component descriptor language utility to minimize the space complexity of the tool. Level of parsing and collaboration level has been updated to reduce time com- plexity of the Timing Power Product tool. Modifying of the programming language for the optimizing the execution timing for the comparisons in the CDL Verilog comparison tool. Change in the file structure and the change in the pattern of include file in main file to minimize the time complexity of the pattern search engine.