Performance Measure of Digital Image Processing on FPGA based Co-processor and DSP Processor

Abstract

As the processing capability of processor increases the computation requirements of application two folds, especially Digital Image Processing algorithms applied on satellite images require tremendous amount of calculations because high resolution images are common in aerial and satellite surveillance, even larger amounts of data are coming in near future. Convolution and cross-correlation are fundamental algorithms required in many image processing tasks, in order to speed up their computation often they are implemented on parallel hardware.

Therefore, to reach constraints imposed, two approaches are possible; one is to use DSP processors having characteristics of SIMD and VLIW architecture, MAC operations which can exploit parallelism. The other is to use hybrid architecture consisting of DSP and FPGA as coprocessor. To implement above mentioned approaches proper DSP need to be selected. As a part of this, some basic image processing algorithms have been studied, implemented and simulated for various leading DSPs. The same algorithms have been implemented for P-IV and the results obtained are compared and analyzed.

The second approach has been implemented for 1D FFT algorithm. As FPGA get rid of pipeline hazards, it can result in faster execution. Here algorithm computation distribution has been suggested which implies implementation of complex multiplications to be implemented in FPGA and other calculations to be done in DSP. For this scenario the speed up is measured and analyzed.