Design of pll and Clock Frequency Generation

Abstract

In recent years, the increasing processing speed of microprocessor motherboards, optical transmission links, intelligent hubs and routers, etc., is pushing the o -chip data rate into the gigabit-per-second range. In the past, high data rates were achieved by massive parallelism, with the disadvantages of increased complexity and cost for the IC package. For this reason, the o -chip data rate should move to the range of Gb/s-per-pin. The processors of today work with the operating frequency of GHz. The Phase Lock Loop acts as a clock generator which multiplies the lower frequency reference clock to match up to the operating frequency of the processor. The objective of this project is to design phase lock loop for clock generation. A Phase Lock Loop designed for the application of clock generation has been real- ized using 0.35 m CMOS technology. The application targets clock generation at speed of 1GHz with input frequency 250MHz. Total power dissipation of the PLL is 94.1mWatt at 3.3V power supply. The jitter is reduced to 5ps using high speed phase frequency detector design with dead zone compensation and charge pump with minimum mismatch in the up and down currents. The design simulation results agree fairly well with the expected results. The pre layout simulation results are evaluated using Eldo Spice Tool and Layout is made using Mentor Graphics Back End Design Tools like IC Station and DA-IC (Design Architect).