IR @ Nirma University
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http://10.1.7.192:80/jspui/handle/123456789/3313| Title: | Design & Simulation of 1.8-V 2-Bit CMOS Flash ADC in 0.35μm |
| Authors: | Bhatt, Khayti Darji, Palak Devashryaee, N. M. |
| Keywords: | Analog-to-Digital Converter (ADC) Flash Low Voltage EC Faculty Paper Faculty Paper ITFEC006 NUCONE NUCONE-2009 |
| Issue Date: | 25-Nov-2009 |
| Publisher: | Institute of Technology, Nirma University, Ahmedabad |
| Citation: | National Conference on Current Trends in Technology, NUCONE-2009, Institute of Technology, Nirma University, Ahmedabad, November 25-27, 2009, Page No. 66-69 |
| Series/Report no.: | ITFEC006-5 |
| Abstract: | CMOS VLSI is progressing at fast rate for decades and dominating most of markets in digital circuit areas. The design and optimization of a high-speed low-voltage CMOS flash analogto- digital converter (ADC) are presented in this paper. This paper describes a 2-bit Flash Analog to digital converter (ADC) implemented in 0.35 μm CMOS TSMC technology. Basic blocks of Flash ADC, comparator, encoder have been implemented. The used analog power supply is only 1.8 V. Power dissipation of the implemented ADC is 2.79mw. and total active area 0.0456 mm2 Simulation result of each block as well as each stage is presented. |
| URI: | http://10.1.7.181:1900/jspui/123456789/3313 |
| Appears in Collections: | Faculty Papers, EC |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ITFEC006-5.pdf | ITFEC006-5 | 291.74 kB | Adobe PDF |  View/Open |
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