Synthesis And APR Of Data-Path Module In Sensor Hub On 32nm/22nm Technology

Abstract

The thesis produced here is the outcome of performing RTL to GDS operation of the industry’s most talked digital circuit, i.e. Sensors. The thesis revolves around the entire SoC design cycle. It explores the entire design cycle step by step starting from RTL coding to the Sign-Off checks. The digital circuit presented here is essentially a datapath circuit which is responsible for taking in the data from general purpose Inputs and giving out the data to Outputs. The most important challenge faced by the industry is Power consumption. The thesis also explores the optimization strategies that can be used to optimize the Power. Together with the Power, TTM(Time To Market) is also an important aspect. The work done also focusses on the optimizing the digital circuit so that the tool is having only the required data to handle and thus the time of execution can be reduced. The Engineering Change Order script is developed to perform the ECO operation which can be used by any tool. The script is a tcl utility which utilizes the result of performing FEV, takes in the original netlist and the modified RTL. The script automatically changes the netlist as per the modified RTL.