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Title: | Modeling SYSTEMC and TLM2.0 models for various elements of PercSense Architecture for Machine learning IP |
Authors: | Patil, Kasturi D. |
Keywords: | EC 2012 Project Report Project Report 2012 EC Project Report EC (Communication) Communication Communication 2012 12MECC 12MECC34 |
Issue Date: | 1-Jun-2014 |
Publisher: | Institute of Technology |
Series/Report no.: | 12MECC34; |
Abstract: | With computing systems these days having the capability of being driven by natural interfaces such as gestures, speech recognition, etc., there is an ever growing need for the systems being built in the future to have more complexity in different domains and hence heavy computing capability to support the underlying Perceptual Computing algorithms. In particular Object detection and recognition of Machine Vision are heavy on compute; also ISP/GPU processors are not very efficient for data manipulation to feed into detection/extraction stages since these stages require data to be extracted from different locations of the integral image. There is a need for efficient extraction of these data elements. Most of the fast implementations of machine vision algorithms for Object recognition make use of Integral Image based (32 bit) processing, and this is not very efficient to be processed on an ISP. The Project aims at improvement of power-performance and alleviating workloads for machine learning algorithms like GMM(Gaussian Mixture Model), KNN(K-Nearest Neighbor), DBNN(Deep Belief Neural Network), CDBNN(Convolutional Deep Belief Neural Network) by providing custom accelerator. The algorithms that have been identified with a common structure for acceleration are GMM for speech based Senone classifier, K Nearest Neighbor (KNN) basedClassifier (Object). Some of the motivating factors for an accelerator of this nature is to be very efficient for a class of Detection/Feature Extraction, Classification and Machine Learning algorithms including Speech based, with the help of this project much better metrics for performance/power/price can be obtained as compared to ISP/GPU based general purpose based vector DSP systems, and this proposed architecture is highly scalable and configurable. |
URI: | http://hdl.handle.net/123456789/4696 |
Appears in Collections: | Dissertation, EC (Communication) |
Files in This Item:
File | Description | Size | Format | |
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12MECC34.pdf | 12MECC34 | 1.25 MB | Adobe PDF | ![]() View/Open |
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