Effiecent Fe Methodology For Rtl Integration In Large CPU Design

Abstract

RTL (register transfer level) integration is an important part of a VLSI design flow. It basically define the quality of the full chip system. Also in large CPU design, whole design are partitioned in different parts to reduce the complexity of the design and at the end all individual RTL logic are integrated to get full chip design. Thus for good quality and well featured chip we need to have a good quality RTL integration in our design. This can be achieved by having well defined FE (front end) methodology or flow. This report will give different FE flow example for different design or application and will explain in detail how we can modify the flow for getting better and verified RTL integration at the end. It will also demonstrate some example which will explain how proper FE methodology can reduce the initial bugs in the design. At the end will also explain the efficient, simple and much faster method for testing the system/tool functionality.