Study and Analysis of SRAM Memory Compiler and Characterization

Abstract

As process technologies shrink, the size and number of memories on a chip are constantly increasing and memory designs become a more significant part of the overall system performance, efficiency, and cost. Random-Access Memories can be time consuming and tedious to custom design, and there are not many options for automating this process. Process design kits from foundries and vendors do not include memory compilers and commercial solutions require expensive licenses and are often un-modifiable and process specific. This thesis introduces Memory compiler, and its characterization methodology. The main objective of this project is to by providing a flexible and portable platform for generating and verifying memory designs across different technology node. Currently, the compiler generates Spice netlists for single port SRAM’s using the 28nm foundry, and provides timing/power characterization through Spice simulation. Memory Compiler can be parameterized by number of words, number of bits per word, desired aspect ratio, number of sub banks, degree of column muxing, etc. Area, delay, and energy consumption complex function of design parameters and generation algorithm worth experimenting with design space.