Error Resilience In Case Of Test Data Compression Technique For IP Core Based Soc

Abstract

The fault coverage is the major quality criteria for any test data. Any bit flip in test data can reduce the fault coverage and hence yield. As per recent trends, use of preprocessed and compressed test data has been common for testing of IP core based SoC. The bit flip in such data can be more dangerous to fault coverage. Further, the hidden structure of IP core does not allow the system integrator to analyze the effect of bit flip on fault coverage. In this scenario, it is utmost necessary to make the test data compression method error resilient. In this paper, we have proposed a method to make test data error resilience. Its effect on % compression and test application time is calculated using highly cited ISCAS89 benchmark circuits. Also the on-chip decoder required for error resilient test data is proposed and corresponding results for area-overhead is shown.