Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/5976
Title: Verification Component Development for Interlaken Protocol
Authors: Rabadiya, Vipul
Keywords: EC 2013
Project Report
Project Report 2013
EC Project Report
EC (VLSI)
VLSI
VLSI 2013
13MEC
13MECV
13MECV22
Issue Date: 1-Jun-2015
Publisher: Institute of Technology
Series/Report no.: 13MECV22;
Abstract: Interlaken protocol is a networking protocol, which transmit data in Gbps speed. Interlaken is a high speed interconnect protocol with high bandwidth and easier packet transfers. Interlaken also uses serial links for a logical connection between components with backpressure capability, logical channels and data-integrity. Advantage of interlaken protocol is high speed, we can use multiple number of logical channel, also can used large number of lanes. Interlaken has also more secure with crc24, crc32 error checking logic. Interlaken protocol is verify by using UVM with system verilog coding, in verification, verify the DUT of design by designer engineer. Implement same DUT functionality and compare both logic for verification.
URI: http://hdl.handle.net/123456789/5976
Appears in Collections:Dissertation, EC (VLSI)

Files in This Item:
File Description SizeFormat 
13MECV22.pdf13MECV221.28 MBAdobe PDFThumbnail
View/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.