Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/6652
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dc.contributor.authorSabalpara, Mrugeshkumar-
dc.date.accessioned2016-07-15T05:48:02Z-
dc.date.available2016-07-15T05:48:02Z-
dc.date.issued2016-06-01-
dc.identifier.urihttp://hdl.handle.net/123456789/6652-
dc.description.abstractSoC are large designs made by combining other large designs. A typical SoC has many communication pathways and a large amount of parallel activity. In order to debug these kinds of designs effectively new approaches must be taken. We discusses the require- ments for effective debug in the face of today's large SoCs, outlining real world example and making some recommendations for easier solutions. This includes transaction based debug, with "connected" transactions. While designing SoC's it also required to view details in depth of part. Zoom Network Diagram viewer is the application which will do this for us.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries14MCEC22;-
dc.subjectComputer 2014en_US
dc.subjectProject Report 2014en_US
dc.subjectComputer Project Reporten_US
dc.subjectProject Reporten_US
dc.subject14MCEen_US
dc.subject14MCECen_US
dc.subject14MCEC22en_US
dc.titleDeveloping Transaction Level Visualization Features For Accelerating Pre-Silicon Debugen_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, CE

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