Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/6652
Title: | Developing Transaction Level Visualization Features For Accelerating Pre-Silicon Debug |
Authors: | Sabalpara, Mrugeshkumar |
Keywords: | Computer 2014 Project Report 2014 Computer Project Report Project Report 14MCE 14MCEC 14MCEC22 |
Issue Date: | 1-Jun-2016 |
Publisher: | Institute of Technology |
Series/Report no.: | 14MCEC22; |
Abstract: | SoC are large designs made by combining other large designs. A typical SoC has many communication pathways and a large amount of parallel activity. In order to debug these kinds of designs effectively new approaches must be taken. We discusses the require- ments for effective debug in the face of today's large SoCs, outlining real world example and making some recommendations for easier solutions. This includes transaction based debug, with "connected" transactions. While designing SoC's it also required to view details in depth of part. Zoom Network Diagram viewer is the application which will do this for us. |
URI: | http://hdl.handle.net/123456789/6652 |
Appears in Collections: | Dissertation, CE |
Files in This Item:
File | Description | Size | Format | |
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14MCEC22.pdf | 14MCEC22 | 2.04 MB | Adobe PDF | ![]() View/Open |
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