Enhancement of HDL Based Memory Models

Abstract

As process of fabrication technologies advances, chip complexity increases and the design flow becomes more iterative. Iterations in the design flow cost money, time and engineering resources that adversely affect the time to market and cost of the devices being designed. This report deals with the development of a generic HDL models and describes the validation process and need for automation of validation environment of behavioral memory models. The project deals with Development of SP, ROM, p-REG & DPREG behavioral models and the use of SV verification environment to validate those behavioral models and using Shell Scripts to automate the validation process. The technology does affect the physical level of the design, but functionality does not change. The customer’s needs affect the model structure and the functionality, not the technology. Thus we always prefer that the given model works for the technology, not on that technology.