Developing Arm Architecture Verification Tools and Solutions

Abstract

Processor architecture verification is the process of uncovering bugs in the design of the processor.The ultimate goal of architectural verification is to deliver the design to market as bug free as possible. It is one of the biggest challenge industry is facing today, as the verification effort is often more than the design effort. "Random Instruction Sequencer (RIS)" tools are most commonly used across the processor design industry for verification and validation of processor design. Thus developing RIS tools would simplify the process of processor design verification which may prove helpful to considerably reduce time to product. The work presented here introduces a unified target configuration generation tool, for auto generation of architecture configuration files used to configure RIS tool. It achieves significant reduction in resource utilization by automating the process of configuration file generation which is being hand coded otherwise. It also includes development of Pre-generation and Post-generation Quality Assurance Tools for the MP RIS Tool which is used for verification of multi-processor environment. The Pre-generation QA tool discards the invalid test cases before generation and hence increases the efficiency of the MP RIS Tool by saving time and resources being used to generate invalid test cases. Whereas the Post-generation QA tool does the analysis of the generated test case to subsequently reduce the percentage of overhead instructions added compared to actually required instructions in a generated test case.