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DC Field | Value | Language |
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dc.contributor.author | Pathak, Anchal Kumar | - |
dc.date.accessioned | 2020-08-14T08:25:35Z | - |
dc.date.available | 2020-08-14T08:25:35Z | - |
dc.date.issued | 2009-06-01 | - |
dc.identifier.uri | http://10.1.7.192:80/jspui/handle/123456789/9316 | - |
dc.description.abstract | This thesis presents a six-transistor SRAM in given nm technology and 1v supply intended for advanced microprocessor cache application with optimal driver delay design Subsequently, the impact of mismatch and process variation on both standard 6T and proposed asymmetric 6TSRAM cells is investigated. Eventually, the cells are compared regarding the voltage scalability, stability, and tolerability to variations in process parameters .Different stage drivers with different fan-out to drive read and write signal from bit-cell with optimal delay design is also covered. Apart from this Memory Compiler basics with different instance generation will also be covered. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 07MEC003; | - |
dc.subject | EC 2007 | en_US |
dc.subject | Project Report 2007 | en_US |
dc.subject | EC Project Report | en_US |
dc.subject | Project Report | en_US |
dc.subject | 07MEC | en_US |
dc.subject | 07MEC003 | en_US |
dc.subject | VLSI | en_US |
dc.subject | VLSI 2007 | en_US |
dc.title | Analysis of SRAM 6T Cell, Driver And Memory Compiler | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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07MEC003.pdf | 07MEC003 | 1 MB | Adobe PDF | ![]() View/Open |
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