Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/9316
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dc.contributor.authorPathak, Anchal Kumar-
dc.date.accessioned2020-08-14T08:25:35Z-
dc.date.available2020-08-14T08:25:35Z-
dc.date.issued2009-06-01-
dc.identifier.urihttp://10.1.7.192:80/jspui/handle/123456789/9316-
dc.description.abstractThis thesis presents a six-transistor SRAM in given nm technology and 1v supply intended for advanced microprocessor cache application with optimal driver delay design Subsequently, the impact of mismatch and process variation on both standard 6T and proposed asymmetric 6TSRAM cells is investigated. Eventually, the cells are compared regarding the voltage scalability, stability, and tolerability to variations in process parameters .Different stage drivers with different fan-out to drive read and write signal from bit-cell with optimal delay design is also covered. Apart from this Memory Compiler basics with different instance generation will also be covered.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries07MEC003;-
dc.subjectEC 2007en_US
dc.subjectProject Report 2007en_US
dc.subjectEC Project Reporten_US
dc.subjectProject Reporten_US
dc.subject07MECen_US
dc.subject07MEC003en_US
dc.subjectVLSIen_US
dc.subjectVLSI 2007en_US
dc.titleAnalysis of SRAM 6T Cell, Driver And Memory Compileren_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, EC (VLSI)

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