Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/9316
Title: Analysis of SRAM 6T Cell, Driver And Memory Compiler
Authors: Pathak, Anchal Kumar
Keywords: EC 2007
Project Report 2007
EC Project Report
Project Report
07MEC
07MEC003
VLSI
VLSI 2007
Issue Date: 1-Jun-2009
Publisher: Institute of Technology
Series/Report no.: 07MEC003;
Abstract: This thesis presents a six-transistor SRAM in given nm technology and 1v supply intended for advanced microprocessor cache application with optimal driver delay design Subsequently, the impact of mismatch and process variation on both standard 6T and proposed asymmetric 6TSRAM cells is investigated. Eventually, the cells are compared regarding the voltage scalability, stability, and tolerability to variations in process parameters .Different stage drivers with different fan-out to drive read and write signal from bit-cell with optimal delay design is also covered. Apart from this Memory Compiler basics with different instance generation will also be covered.
URI: http://10.1.7.192:80/jspui/handle/123456789/9316
Appears in Collections:Dissertation, EC (VLSI)

Files in This Item:
File Description SizeFormat 
07MEC003.pdf07MEC0031 MBAdobe PDFThumbnail
View/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.