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Browsing by Subject EC 2011

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Showing results 1 to 20 of 35  next >
PreviewIssue DateTitleAuthor(s)
11MECC07.pdf.jpg1-Jun-2013Automation of IP CAD View ValidationKotadia, Amit
11MECV18.pdf.jpg1-Jun-2013Configuration Register ValidationUdani, Kausshalee A.
11MECV07.pdf.jpg1-Jun-2013Cryptography Algorithm On Reconfigurable HardwareMansur, Riyaz L.
11MECC01.pdf.jpg1-Jun-2013DAPTOOL Enhancement in iDEN (Integrated Digital Enhanced Network)Bhatt, Hardik V.
11MECV01.pdf.jpg1-Jun-2013Design and Development of Memory Scrambling Checker and Improvement in Memory Characterization Flow for Advanced Technology NodesAdesara, Ankit M.
11MECC18.pdf.jpg1-Jun-2013Design and Implementation of Automatic Modulation Recognition System for Software De ned RadioVipani, Maulik M.
11MECC04.pdf.jpg1-Jun-2013Design and Optimization of Microstrip Patch Antennas using Adaptive Neuro-Fuzzy Inference System (ANFIS)Ghadiya, Jignesh Raghavbhai
11MECV08.pdf.jpg1-Jun-2013Design and Simulation of 2.4 GHz Frequency SynthesizerPatel, Dharmesh Babubhai
11MECV15.pdf.jpg1-Jun-2013Design and Simulation of Current Mirror CircuitsSaiyed, FaizAhmed J.
11MECV16.pdf.jpg1-Jun-2013Design and Simulation of Third Generation Current Conveyor and Its ApplicationShah, Payal D.
11MECV09.pdf.jpg1-Jun-2013Design of Parallel Architecture For Correlator using FPGAPatel, Dhaval D.
11MECV03.pdf.jpg1-Jun-2013Development of DFT for TMC IP in SoCChotaliya, Miten Kaushikbhai
11MECV06.pdf.jpg1-Jun-2013Development of Veri cation Environment for PMB (Process monitoring Box) in nm TechnologyKansagra, Keyurkumar K.
11MECV14.pdf.jpg1-Jun-2013Development of Verification IP for LINFlex Controller using UVMPatel, Vivek Jayeshbhai
11MECV12.pdf.jpg1-Jun-2013Formal Equivalence Verification of Phase Locked LoopsPatel, Jigar Babulal
11MECC16.pdf.jpg1-Jun-2013GOP (Graphics Output Protocol) Configuration Driver for BIOSSolanki, Digant H.
11MECV13.pdf.jpg1-Jun-2013Implementation of DFT in Automotive ChipPatel, Mehul
11MECV11.pdf.jpg1-Jun-2013Improvements to Intel's Analog IP Design Flows at Sub 32nm or below Process NodesPatel, Jaydeep
11MECC06.pdf.jpg1-Jun-2013Interconnect Performance Estimation TechniquesJoshi, Pranavkumar Mansukhlal
11MECC10.pdf.jpg1-Jun-2013LMT Automation and Functional Testing of Dispatch Application ProcessorJoshi, Parul
Showing results 1 to 20 of 35  next >