Browsing by Subject VLSI 2006

Jump to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:  
Showing results 1 to 16 of 16
PreviewIssue DateTitleAuthor(s)
06MEC003.pdf.jpg1-Jun-2008Analysis of components of BBIC-RFIC Interface in communication standard such as WiMAX and LTEBhatt, Jui B.
06MEC012.pdf.jpg1-Jun-2008Architecture Evaluation for Programmable Logic (90nm/65nm)Patel, Mehul I.
06MEC006.pdf.jpg1-Jun-2008Architecture Evaluation for Programmable Logic in 65NMHirani, Chandresh
06MEC015.pdf.jpg1-Jun-2008Characterization, Validation & Design tuning of CMOS Memory in 0.18micron TechnologyPandey, Sailesh
06MEC007.pdf.jpg1-Jun-2008Design & Simulation Of Wide Swing Folded Cascode OTA Using 0.35 ΜM CMOS TechnologyShah, Kehul
06MEC018.pdf.jpg1-Jun-2008Design and Simulation of current feed back amplifier using 0.35 nm CMOS TechnologyPatel, Nilesh D.
06MEC004.pdf.jpg1-Jun-2008Design and Simulation of High Speed Delta-Sigma ADC in Deep Sub-micron TechnologyGajjar, Rakesh
06MEC010.pdf.jpg1-Jun-2008Design and Simulation of Programmable Switched-capacitor Filter using 0.35μm CMOS TechnologyParmar, Jayesh P.
06MEC002.pdf.jpg1-Jun-2008Design Of A 64-Bit Floating Point Co- ProcessorBhatt, Hetal
06MEC001.pdf.jpg1-Jun-2008Design of CMOS I/O Library Cell in 65 nm TechnologyKumar, Ankush
06MEC019.pdf.jpg1-Jun-2008Evaluation of specific features of CAD tool (APACHE) for CMOS Standard Cell FlowSharma, Anand
06MEC013.pdf.jpg1-Jun-2008Front End Development of I/O Libraries for Different NVM TechnologiesPatel, Naresh
06MEC009.pdf.jpg1-Jun-2008Verification Of Behavioral Models for Analog IP’sParekh, Hardik
06MEC017.pdf.jpg1-Jun-2008Verification of D3G Module for Wireless Chip in 65nmVora, Snehal
06MEC011.pdf.jpg1-Jun-2008Verification of RAM at Soc and Register Automation of SoCPatel, Ankit
06MEC014.pdf.jpg1-Jun-2008VLSI Design of Discrete Wavelet Transform using Distributed ArithmaticSingh, Rajendra Bahadur