Browsing by Author Dhare, Vaishali

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Showing results 1 to 13 of 13
PreviewIssue DateTitleAuthor(s)
ITFEC022-9.pdf.jpgApr-2014Advanced ATPG Based On Fan, Testability Measures And Fault ReductionDhare, Vaishali; Mehta, Usha
ITFEC022-7.pdf.jpg25-Nov-2009Application of CORDIC Algorithm for Sine-Cosine ComputationJoshipura, Himali; Dhare, Vaishali; Mehta, Usha
ITFEC022-1.pdf.jpg2007CAMEL: Customized Application for Mobile Enhanced LogicDhare, Vaishali
ITFEC022-6.pdf.jpg25-Nov-2009CMOS Differential Voltage Current Conveyor using 0.25μm TechnologyDhare, Vaishali; Naik, Amisha
ITFEC022-4.pdf.jpg23-Apr-2010Controllability and Observability Algorithm for 10-fanin-fanout Combinational CircuitsDhare, Vaishali; Mehta, Usha
ITFEC022-12.pdf.jpgMar-2016Defect Analysis Of Quantum-Dot Cellular Automata Combinational Circuit Using HDLQDhare, Vaishali; Mehta, Usha
ITFEC022-11.pdf.jpg26-Jun-2015Defect characterization and testing of QCA devices and circuits: A surveyDhare, Vaishali; Mehta, Usha
ITFEC022-5.pdf.jpg23-Jul-2010Development of Controllability Observability Aided Combinational ATPG with Fault ReductionDhare, Vaishali; Mehta, Usha
ITFEC022-10.pdf.jpg19-Dec-2015Fault Analysis of QCA Combinational Circuit at Layout & Logic LevelDhare, Vaishali; Mehta, Usha
ITFEC022-8.pdf.jpgFeb-2013Implementation Of Compaction Algorithm For ATPG Generated Partially Specified Test DataDhare, Vaishali; Mehta, Usha
ITFEC010-15.pdf.jpg2013Logic Optimization Algorithm based on Shannon’s Expansion: Reduction in Area, Power and Delay for Pass Gate ImplementationMehta, Usha; Dhare, Vaishali; Parmar, Harikrishna; Shah, Rahul A.
ITFEC022-3.pdf.jpg9-Dec-2010Multiple Input Single Output Filters Using CMOS DVCC in 0.25μm TechnologyDhare, Vaishali; Naik, Amisha
ITFEC022-2.pdf.jpgJun-2010Object Oriented Implementation of Combinational Controllability and Observability AlgorithmsDhare, Vaishali; Mehta, Usha