Browsing by Subject VLSI 2018

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Showing results 1 to 19 of 19
PreviewIssue DateTitleAuthor(s)
18MECV05.pdf.jpg1-Jun-2020Analysis of Signatures for Observation IP and updating RTL for non-zero SignaturesGandhi, Sneh
18MECV15.pdf.jpg1-Jun-2020Automate DRC and LVS RunPrajapati, Lalitkumar
18MECV03.pdf.jpg1-Jun-2020Automated Flow to Generate Design Exchange Format for RLS BlockDesai, Priyal
18MECV17.pdf.jpg1-Jun-2020Automatic Test Pattern Generation and Simulation for Multimillion Gates SOCShah, Alisha
18MECV11.pdf.jpg1-Jun-2020Automation to Improve Efficiency in Power AnalysisMishra, Pooja
18MECV12.pdf.jpg1-Jun-2020Boundary Scan VerificationPatel, Krishna
18MECV18.pdf.jpg1-Jun-2020Comparative Analysis of UVM TLM1 with TLM2 InterfacesSingh, Divanshi
18MECV06.pdf.jpg1-Jun-2020Full Chip Timing Analysis: Scope for efciency ImprovementChauhan, Hemal
18MECV14.pdf.jpg1-Jun-2020Implementation of safety and security features in Network-on-ChipPatel, Vishruti
18MECV04.pdf.jpg1-Jun-2020Interconnect Optimization For Dynamic Power ReductionKothari, Foram
18MECV08.pdf.jpg1-Jun-2020Low Power Veri cation of Data Manipulation IP using UPF MethodologyKoshiya, Jatinkumar
18MECV16.pdf.jpg1-Jun-2020Magillem based SOC integrationPrasad, Rishabh
18MECV02.pdf.jpg1-Jun-2020Metal Layer Pattern DetectionBhavsar, Tithi
18MECV19.pdf.jpg1-Jun-2020Overall Execution Efficiency Improvement in PLL DeliverablesVaghela, Divyarajsinh
18MECV10.pdf.jpg1-Jun-2020Post Silicon Validation of DC-DC Boost Converter Analog IPPatel, Mayurkumar
18MECV01.pdf.jpg1-Jun-2020Power – Grid Creation, Analysis and Evaluation on Industry Technology NodesBhatiya, Hepi
18MECV07.pdf.jpg1-Jun-2020SystemVerilog Assertions based Arbiter VerificationSharma, Khyati
18MECV09.pdf.jpg1-Jun-2020Validation of Machine Learning Accelerator IPJain, Kushal
18MECV13.pdf.jpg1-Jun-2020Verification of Ethernet based IP/Subsystem in Smart NICPatel, Mit