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PreviewIssue DateTitleAuthor(s)
ITFEC007-1.pdf.jpg8-Dec-2011Analysis and Design of Flash Analog to Digital Converter for Ultra Wide Band ApplicationKanodiya, Piyush.V.; Naik, Amisha; Devashrayee, N. M.
TT000082.pdf.jpg2018Analysis and Design of High Speed Low Offset Power Efficient Dynamic CMOS Comparator in 180nm TechnologyGandhi, Priyeshkumar Pratapbhai
ITFEC010-7.pdf.jpg8-Dec-2011Artificial Intelligence Based Scan Vector Reordering for Capture Power MinimizationMehta, Usha; Dasgupta, Kankar S.; Devashrayee, N. M.; Parmar, Harikrishna
ITFEC006-2.pdf.jpg9-Dec-2010Characterization & Comparative Analysis of High Speed CMOS Comparator for Pipelined ADCGandhi, Priyesh P.; Devashryaee, N. M.
ITFEC010-5.pdf.jpg6-Dec-2010Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area OverheadMehta, Usha; Dasgupta, K. S.; Devashrayee, N. M.
ITFEC006-5.pdf.jpg25-Nov-2009Design & Simulation of 1.8-V 2-Bit CMOS Flash ADC in 0.35μmBhatt, Khayti; Darji, Palak; Devashryaee, N. M.
ITFEC024-10.pdf.jpg2013Design and Analysis of Source Current Effect on Preamplifier-Positive Feedback-based CMOS Comparator Using 90 nm TechnologySavani, Vijay G.; Devashrayee, N. M.
ITFEC006-4.pdf.jpg25-Nov-2009Design and Simulation of 3-Stage Pipeline ADCPatel, Manish I.; Patel, Shail K.; Devashrayee, N. M.
TT000069.pdf.jpg2018Design of a Low Voltage, Low Power and High Speed CMOS ComparatorSavani, Vijay Gopalbhai
TT000068.pdf.jpg2018Design of High Performance Low Noise AmplifierMecwan, Akash Isudas
ITFEC006-9.pdf.jpgApr-2012Design Simulation And Characterisation Of Op-Amp Based 3 Bit R-2r Segmented DacsSoni, Rajanikant; Amin, Gireeja; Devashrayee, N. M.; Mehta, Usha
ITFEC007-2.pdf.jpg9-Dec-2010Effect of Parameter Variation on OTA based Second Generation Current conveyor (CCII)Naik, Amisha; Devashrayee, N. M.
ITFEC010-27.pdf.jpg29-Sep-2010Hamming Distance Based 2-D Reordering With Power Efficient Don’t Care Bit Filling: Optimizing the Test Data Compression MethodMehta, Usha; Devashrayee, N. M.; Dasgupta, K. S
ITFEC010-25.pdf.jpgDec-2010Hamming Distance Based Distributed Scan Chain Reordering For Test Power OptimizationMehta, Usha; Dasgupta, K. S.; Devashrayee, N. M.; Choksi, Kushal
ITFEC006-7.pdf.jpgFeb-2014The Influence of Stabilisers on Resistance to Gamma Radiation for Epoxy based Polymeric Composite MaterialSaiyad, Mamta; Devashrayee, N. M.; Mewada, R. K.
ITFEC006-3.pdf.jpg25-Nov-2009Low Noise Telescopic OTAShah, K. A.; Bhatt, H. G.; Devashrayee, N. M.
ITFEC006-1.pdf.jpg9-Dec-2010Low Power and Low Jitter PLL for Clock GeneratorThakore, Kruti P.; Devashrayee, N. M.
ITFEC006-6.pdf.jpg25-Nov-2009MOS Current Mode Logic for High Speed Communication Using 130nm TechnologyOza, Shruti; Devashrayee, N. M.
ITFEC024-13.pdf.jpg2014Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm TechnologySavani, Vijay G.; Devashrayee, N. M.
ITFEC004-2.pdf.jpg8-Dec-2011Scalable LEON 3 based SoC for Multiple Floating Point OperationsGajjar, Nagendra; Devahsrayee, N. M.; Dasgupta, K. S.
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