1. DSpace at Nirma University
  2. 02. Institute of Technology
  3. Electronics and Communication Engineering Department

Dissertation, EC (VLSI) : [423] Collection home page

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Collection's Items (Sorted by Submit Date in Descending order): 101 to 120 of 423
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PreviewIssue DateTitleAuthor(s)
17MECV14.pdf.jpg1-Jun-2019Design and Analysis of Frequency SynthesizerRamanuj, Parth
17MECV13.pdf.jpg1-Jun-2019Layout Convergence in Lower Technology NodesParikh, Yesha
17MECV12.pdf.jpg1-Jun-2019Frontend Validation of Memory Subsystem in SoCPandya, Parth
17MECV11.pdf.jpg1-Jun-2019Physical Design Implementation and Reliability Verification of an Industry Standard IP CorePandit, Shivam
17MECV10.pdf.jpg1-Jun-2019Optimization of a Component IP within an Infrastructure SubsystemMitra, Ronita
17MECV09.pdf.jpg1-Jun-2019Analysis and Development of Standard Cell Layout in FDSOI TechnologyMacwan, Madhvi
17MECV08.pdf.jpg1-Jun-2019Automation Techniques to Improve Custom Layout Productivity and Process Design Kit QualityKapoor, Sejal
17MECV07.pdf.jpg1-Jun-2019Debug Feature Implementation on Intel’s Next Generation Client SoCJirawala, Ankush Mahavirchand
17MECV06.pdf.jpg1-Jun-2019Pre-Silicon Verification and Debug Improvements in Server Class IPsDholakiya, Harsh
17MECV05.pdf.jpg1-Jun-2019Customized Routing Optimization Flow To Fix Timing Violations in Ultra Deep Sub Micron TechnologyDeshkar, Omkar
17MECV04.pdf.jpg1-Jun-2019Validation of Performance Monitoring Architecture in Fullchip EnvironmentDesai, Prakruti
17MECV03.pdf.jpg1-Jun-20196T-SRAM Cell Leakage Current Analysis & Self-Timing Circuit In MemoryChauhan, Dhruvkumar
17MECV02.pdf.jpg1-Jun-2019Performance and Power Optimization in High Speed DesignArvind
17MECV01.pdf.jpg1-Jun-2019Timevision Exploration and SoC Implementation FlowLasod, Anshul
16MECV13.pdf.jpg1-Jun-2019Timing Closure of Partitions for Lower Technology NodesRao, Meenakshi
16MECV30.pdf.jpg1-Jun-2018Radiation Hardening For CMOS SRAMSolanki, Darshan
16MECV29.pdf.jpg1-Jun-2018Implementation Methodology Of On-chip High Speed InterconnectZala, Priyanka
16MECV28.pdf.jpg1-Jun-2018Pre-Silicon Verification of Design For Debug Logic in SoCShukla, Vanisha
16MECV27.pdf.jpg1-Jun-2018Implementation of SPI/I2C/Mux-Demux logic for MULTIDUT Setup for SoC CharacterizationVaidya, Chirag Hemantkumar
16MECV26.pdf.jpg1-Jun-2018Implementation Of 32 Bit SPARC Processor On 180nm CMOS ProcessSingh, Aishwarya
Collection's Items (Sorted by Submit Date in Descending order): 101 to 120 of 423
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