1. DSpace at Nirma University
  2. 02. Institute of Technology
  3. Electronics and Communication Engineering Department

Dissertation, EC (VLSI) : [423] Collection home page

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Collection's Items (Sorted by Submit Date in Descending order): 121 to 140 of 423
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PreviewIssue DateTitleAuthor(s)
16MECV24.pdf.jpg1-Jun-2018Implementation of Cortex A Series Processor On FinFET TechnologyChoudhary, Shivani
16MECV23.pdf.jpg1-Jun-2018Robust Timing Analysis & Modelling of Custom High Speed Serial IO BlocksShah, Darshan Sunil
16MECV22.pdf.jpg1-Jun-2018ASIC Design and Implementation of 4 Bit DACSayani, Mahapatra
16MECV21.pdf.jpg1-Jun-2018Accelerating the Speed of Integrating IPs into SoCSapovadia, Dhara Mukeshbhai
16MECV20.pdf.jpg1-Jun-2018Configurable RTL Generation Using AutomationRathore, Ritu
16MECV19.pdf.jpg1-Jun-2018Improvements in PHY Low Power Analysis and VerificationKant, Ravindra
16MECV18.pdf.jpg1-Jun-2018Building Testchip for Enabling Faster SoC FlowRamanuj, Zeel Ghanshyambhai
16MECV17.pdf.jpg1-Jun-2018PCIe Physical Layer Verification using SystemVerilog & UVMPatel, Jinal
16MECV16.pdf.jpg1-Jun-2018Comparative Analysis and Evaluation Of Different CMOS TechnologiesGodre, Ocean
16MECV15.pdf.jpg1-Jun-2018Modeling and Optimization Techniques for Yield-Aware SRAM Pre-Silicon TuningNagaria, Yash
16MECV14.pdf.jpg1-Jun-2018Automatic Gain Control Amplifier for Biomedical ApplicationsModi, Bhavik
16MECV12.pdf.jpg1-Jun-2018Read/write Assist: Analysis of The Data Stability Across High Desnsity Sram Cells in Lower VoltageMachhi, Advaitkumar D.
16MECV11.pdf.jpg1-Jun-2018A Built-in Self-Test with Design for Testability Support for Embedded SRAMPannalal, Khatik Bhagvan
16MECV10.pdf.jpg1-Jun-2018Memory BIST Implementation and ValidationJaviya, Mitali Harishbhai
16MECV09.pdf.jpg1-Jun-2018SoC Security and Debugging through CR Management and AccessJani, Khyati Ashok
16MECV08.pdf.jpg1-Jun-2018Deploying and Improving Clock Domain Crossing Verification Techniques for SoCsJain, Sachin Sanjaykumar
16MECV07.pdf.jpg1-Jun-2018Improvements in PHY Timing Analysis Methodology to Achieve High Turn Around Time and Better QualityGurjar, Kishan
16MECV05.pdf.jpg1-Jun-2018Designing and Timing Analysis of Decision Feedback Equalizer in ReceiverFulvani, Anita
16MECV04.pdf.jpg1-Jun-2018Automated Flow to fix Semi-custom Layout DRC in Ultra-Deep-Submicron TechnologyDave, Prachi
15MECV30.pdf.jpg1-Jun-2017Mixed Signal Implementation in Advanced Node for Cadence PlatformVegad, Krutarth Shantibhai
Collection's Items (Sorted by Submit Date in Descending order): 121 to 140 of 423
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